Data Sheet
Preliminary
PowerPC 970FX
For reliable operation, it is highly recommended that the unused inputs be connected to an appropriate
signal level. For example:
• Unused active low inputs should be tied to VDD
.
• Multiple unused active high inputs may be ganged together for convenience.
• Unused active high inputs should be connected to GND.
• Multiple unused active low inputs may be ganged together for convenience.
• All no-connect (NC) signals must remain unconnected.
Power and ground connections must be made to all external VDD and GND pins of the PowerPC 970FX.
Table 5-6. PowerPC 970FX Debug/Bringup Pin Settings and Information
Resistor
Pull Up/Down
Setting
1
1
Pin Name
Pin Location
In/Out/BiDi/JTAG
Comments
(For Normal
Operation)
AVP_RESET
W23
AC16
AC15
AA22
In
In
In
In
Up
Down
Down
Up
C1_UND_GLOBAL
C2_UND_GLOBAL
GPULDBG
arbitrates between I2C and
JTAG.
I2CGO
N22
Out
Up
TBEN
AD17
AD21
AB21
AD13
AD22
N21
In
Down
Down
Down
Down
Down
Down
—
TCK
In-JTAG
In-JTAG
Out-JTAG
In-JTAG
In
JTAG – Test Clock
TDI
JTAG – Test Data In
JTAG – Test Data Out
JTAG – Test Mode Select
TDO
TMS
TRIGGERIN
TRIGGEROUT
N19
Out
.
Not needed – HRESET
does the cop reset function.
Tie high and leave
TRST
W20
In-JTAG
Up
unconnected.
Notes:
1. BiDi = Bidirectional
2. Pullups should use a 10K resistor to OV . Pulldowns should use a 10K resistor to GND.
DD
2
3. For I C or JTAG operation refer to Section 3.10.3
System Design Information
Page 63 of 74
October 14, 2005
IBM [ IBM ]
