Data Sheet
Preliminary
PowerPC 970FX
5.2.3 Typical PLL and SYSCLK Configurations
Table 5-3 provides a few examples of typical system configurations.
Table 5-3. System Configuration - Typical Examples of Pin Settings
BUS_CFG(0:2)
Pins
PLL_RANGE(1:0)
Pins
SYSCLK,SYSCLK
Frequency
System Configuration
PLL_MULT Pin
2.2 GHz core, 1100 MHz EIO
2.2 GHz core, 733 MHz EIO
2.0 GHz core, 1000 MHz EIO
2.0 GHz core, 667 MHz EIO
1.8 GHz Core, 900 MHz EIO
1.8 GHz core, 600 MHz EIO
1.6 GHz core, 800 MHz EIO
1.6 GHz core, 533 MHz EIO
1.4 GHz core, 700 MHz EIO
1.4 GHz core, 467 MHz EIO
1.2 GHz core, 600MHz EIO
1.0 GHz core, 500 MHz EIO
000 (2:1)
001 (3:1)
000 (2:1)
001 (3:1)
000 (2:1)
001 (3:1)
000 (2:1)
001 (3:1)
000 (2:1)
001 (3:1)
000 (2:1)
000 (2:1)
10
10
10
10
01
01
01
01
01
01
00
00
1
0
1
0
1
0
1
0
1
0
1
1
275MHz
183.3MHz
250MHz
167MHz
225MHz
150MHz
200MHz
133MHz
175MHz
116.7MHz
150MHz
125MHz
System Design Information
Page 59 of 74
October 14, 2005
IBM [ IBM ]
