Data Sheet
PowerPC 970FX
Preliminary
3.5 Processor Interconnect Specifications
3.5.1 Electrical and Physical Specifications
3.5.1.1 Source Synchronous Bus (SSB)
Figure 3-3 depicts a representative block diagram of an SSB for a PowerPC 970FX Processor Interconnect
implementation. Each SSB consists of three major subsections: the drive side, the module-to-module inter-
connect, and the receive side. Data is first either Balance-Coding-Method (BCM) encoded or checksummed,
then clock-phase multiplexed, and finally launched from the drive side onto the module interconnect. The
receive side includes far-end termination and circuitry to demultiplex, deskew data, align clocks, and synchro-
nize the received data.
Figure 3-3. Block Diagram of an SSB for a Processor Interconnect Implementation
TERM
D
R
TERM
D
R
Clock
Dist.
Clock
Source
TERM
R
D
Drive Side
Interconnect
Receive Side
NOTE: The PI on-chip termination network can consume several watts of power. To minimize power consumption, It may be
possible to disable the on-chip termination through careful selection of bus speed and detailed modeling of the board layout.
3.5.1.2 Drive Side Characteristics
Figure 3-4 shows a typical implementation for a single-ended line. The drivers are of the push-pull type with a
nominal impedance (R0 of 20 ohms) that overdrives the line impedance. The nominal swing at the receiver,
terminated with resistance (TR0 of 110 ohms) to each rail, is 13% OVDD to 87% OVDD. R0 is 20 ohms when
the driver is in the low output impedance mode. The 20 ohm setting is suitable for all bus speeds. The
PPC970FX has a 40 ohm nominal output impedance mode that is suitable for bus speeds below 800 MT/s in
some applications.
The maximum skew between any of the outputs is 150 ps at the BGA pin. The maximum interconnect skew
on the card(s) between any two outputs must be less than 150 ps. The interconnect skew on the card(s)
between any two inputs must be less than 300 ps.
Electrical and Thermal Characteristics
October 14, 2005
Page 26 of 74
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