Data Sheet
PowerPC 970FX
Preliminary
Figure 3-1. Clock Differential HSTL Signal
SYSCLK
5
2
4
SYSCLK
3
1
Notes:
The legend for this figure is provided by callout number in Table 3-9.
To determine the processor clock, multiply the SYSCLK by one of the following:
• 12 for PLL_MULT = 0
• 8 for PLL_MULT = 1
For more information about the PLL configuration, see Table 5-2 on page 58.
3.4 Processor-Clock Timing Relationship Between PSYNC and SYSCLK
Table 3-10 and Figure 3-2 provide a description of the processor-clock timing relationship between PSYNC
and SYSCLK.
Table 3-10. Processor-Clock Timing Relationship Between PSYNC and SYSCLK
Value
Call Out
Number
Characteristic
Unit
Minimum Maximum
1
2
3
Setup time
Hold time
t
0.8
0.8
0.8
—
—
—
ns
ns
ns
SETUP
t
HOLD
Guard time
t
GUARD
Note: For a timing diagram, see Figure 3-2 on page 25 .
Electrical and Thermal Characteristics
Page 24 of 74
October 14, 2005
IBM [ IBM ]
