Data Sheet
Preliminary
PowerPC 970FX
3.3 Clock AC Specifications
Table 3-9 provides the clock AC timing specifications as defined in Figure 3-1 Clock Differential HSTL Signal.
Table 3-9. Clock AC Timing Specifications
Value
Call Out
Number
Characteristic
Unit
Notes
Minimum Maximum
—
SYSCLK frequency
100
—
300
75
MHz
ps
ps
V
1, 2, 4
4
—
SYSCLK input jitter (cycle to cycle)
SYSCLK rise and fall time
SYSCLK and SYSCLK input high voltage
SYSCLK and SYSCLK input low voltage
Differential Crossing Point Voltage
Differential voltage
1
—
500
3, 4
4
2
—
OV +0.3
DD
3
-0.3
—
V
4
4
5
0.4 x OV
0.385
—
0.6 x OV
1.6
V
4
DD
DD
V
4,7
4, 6
—
—
PLL lock time
800
µSec
—
—
Duty Cycle
40%
60%
Notes:
1. Important: Processor frequency is determined by PLL_MULT and SYSCLK input frequency. PLL_RANGE(1:0) must be set to
the correct values for expected processor frequency. Consult Table 5-2. PowerPC 970FX PLL Configuration on page 58 for the
allowable frequency range for these pins.
2. PowerPC 970FX minimum processor frequency will be determined by characterization. The minimum frequency is an estimation.
3. Rise and fall times for the SYSCLK inputs are measured from 0.4 to 1.0V.
4. Important: The data in this table is based on simulation and may be revised after hardware characterization.
5. For a timing diagram, see Figure 3-1.
6. Guaranteed by design and not tested.
7. The differential voltage is the minimum peak to peak voltage on both the SYSCLK and SYSCLK pins (similar to what would be
measured with single ended oscilloscope probes).
Electrical and Thermal Characteristics
October 14, 2005
Page 23 of 74
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