Datasheet
PowerPC 970FX RISC Microprocessor
Table 5-8. Input/Output Signal Descriptions (Page 3 of 4)
Pin Name
Width
In/Out
System/Debug Function
Selects the PLL multiplication factor:
Notes
9
PLL_MULT
1
In
‘0’
‘1’
Multiply reference frequency by 12.
Multiply reference frequency by 8.
To select the PLL frequency range, see Table 5-2. PowerPC 970FX
RISC Microprocessor PLL Configuration on page 64.
PLL_RANGE(1:0)
2
In
9
PLLTEST
1
1
3
1
1
1
In
Out
In
For manufacturing test use only.
4
—
—
4
PLLTESTOUT
PROCID(0:2)
PSRO_Enable
PSRO0
For measuring the PLL output (divide by 64).
System: processor ID maximum eight processors
For manufacturing test use only.
Out
Out
In
For manufacturing test use only.
5
PSYNC
System: phase synchronization from North Bridge.
—
System: Phase synchronization signal for observation that proces-
sors are in sync.
PSYNC_OUT
1
Out
—
PULSE_SEL(0:2)
QACK
3
1
In
In
—
—
System: acknowledgment of quiesce from the system.
System: request from the processor to quiesce the system (nap
mode).
QREQ
1
Out
—
RAMSTOP_ENABLE
RI
1
1
1
1
1
2
2
2
2
1
In
In
For manufacturing test use only.
Dedicated manufacturing input.
4
1
SPARE
In/Out
In/Out
In
—
4
SPARE2
SRESET
System: soft reset input.
—
—
—
—
—
4
SRIN(0:1)
In
System: PI snoop response input.
System: PI inverse of snoop response input.
System: PI snoop response output.
System: PI inverse of snoop response output.
For manufacturing test use only.
SRIN(0:1)
In
SROUT(0:1)
SROUT(0:1)
SYNC_ENABLE
Out
Out
In
SYSCLK
SYSCLK
2
In
System reference clock (differential input).
—
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal processor operation.
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2
2. For I C or JTAG operation, the TCK and TDI signals must be pulled down to ground with a 10 kΩ resistor. See Section 3.10.3 on
page 43.
3. Bus ratios 8:1 and 16:1 are not supported for PI Input functionality.
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.
5. This signal should not be connected.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point
immediately behind the module. They should not be connected to GND and V planes.
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7. BiDi = bidirectional. OD = open drain.
8. Using the 4:1 or 12:1 ratio with multiplier of 12 limits the use of power tuning to (frequency)/2.
9. The PLL_MULT and PLL_RANGE(1:0) bits can be overwritten by JTAG commands and the BUS_CFG bits can be changed by
SCOM commands during the POR sequence. See the PowerPC 970FX Power On Reset Application Note for more details
10. Must be pulled down with a 10 kΩ resistor to GND.
11. The TRST signal must be pulled up to OV with a 10 kΩ resistor.
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Version 2.5
System Design Information
Page 73 of 78
March 26, 2007
IBM [ IBM ]
