Datasheet
PowerPC 970FX RISC Microprocessor
5.6 Pullup and Pulldown Recommendations
For reliable operation, it is highly recommended that the unused inputs be connected to an appropriate
signal level. For example:
• Unused active-low inputs should be tied to VDD
.
• Multiple unused active-high inputs can be ganged together for convenience.
• Unused active-high inputs should be connected to GND.
• Multiple unused active-low inputs can be ganged together for convenience.
• All no-connect signals must remain unconnected.
Power and ground connections must be made to all external VDD and GND pins of the PowerPC 970FX.
Table 5-6 provides details about the pin settings and information of the PowerPC 970FX debug and bringup
signals. Table 5-7 on page 70 provides details about the appropriate connections for the PowerPC 970FX
manufacturing test-only signals.
Table 5-6. PowerPC 970FX Debug and Bringup Pin Settings and Information
Pull-Up or Pull-
Down Resistor
1
2
Pin Name
Pin Location
In/Out/BiDi/JTAG
Setting
Comments
(For Normal
Operation)
AVP_RESET
W23
AC16
AC15
AA22
In
In
In
In
Up
Down
Down
Up
C1_UND_GLOBAL
C2_UND_GLOBAL
GPULDBG
2
Arbitrates between I C and
JTAG.
I2CGO
N22
Out
Up
TBEN
AD17
AD21
AB21
AD13
AD22
N21
In
Down
Down
Down
Down
Down
Down
—
TCK
In-JTAG
In-JTAG
Out-JTAG
In-JTAG
In
JTAG – test clock
TDI
JTAG – test data in
JTAG – test data out
JTAG – test mode select
TDO
TMS
TRIGGERIN
TRIGGEROUT
N19
Out
.
Not needed – HRESET per-
forms the Common On-Chip
Processor (COP) reset func-
TRST
W20
In-JTAG
Up
tion. Pulled up to OV by a
DD
10 kΩ resistor.
Notes:
1. BiDi = Bidirectional.
2. Pullups should use a 10 kΩ resistor to OV . Pulldowns should use a 10 kΩ resistor to GND.
DD
2
3. For I C or JTAG operation, see Section 3.10.3 on page 43.
Version 2.5
System Design Information
Page 69 of 78
March 26, 2007
IBM [ IBM ]
