Datasheet
PowerPC 970FX RISC Microprocessor
Table 5-8. Input/Output Signal Descriptions (Page 2 of 4)
Pin Name
C2_UND_GLOBAL
Width
1
In/Out
In
System/Debug Function
Notes
10
Debug: adjusts the C2 clock to internal latches and is not used for
normal operation.
OD
/BiDi
CHKSTOP
1
1
System: checkstop input and output.
7
CKTERM_DIS
In
In
Disable internal termination in clock receiver.
—
CLKIN
CLKIN
2
System: PI clock in; differential clock to the processor.
—
CLKOUT
CLKOUT
2
1
1
Out
In
System: PI differential clock to the bus.
Dedicated manufacturing signal.
—
1
DI2
Debug: Disables the use of the initial alignment procedure (IAP) to
adjust clock skew on the processor interface.
EI_DISABLE
In
—
GPULDBG
HRESET
1
1
In
In
Debug: POR debug mode select.
System: POR.
—
—
OD
2
I2CCK
I2CDT
1
1
System: I C signal clock.
7
7
/BiDi
OD
2
System: I C interface data.
/BiDi
2
I2CGO
1
1
1
1
1
1
1
1
1
1
1
OD
In
Debug: handshake signal to arbitrate JTAG or I C access.
7
—
4
INT
System: external interrupt when low.
For manufacturing test use only.
LSSD_SCAN_ENABLE
KVPRBVDD
In
In
V
test point.
6
DD
KVPRBGND
In
GND test point.
6
LSSD_STOP_ENABLE
LSSD_STOPC2_ENABLE
LSSD_STOPC2STAR_ENABLE
LSSDMODE
In
For manufacturing test use only.
For manufacturing test use only.
For manufacturing test use only.
For manufacturing test use only.
System: machine check interrupt.
Indicates that the PLL has locked.
4
In
4
In
4
In
4
MCP)
In
—
—
PLL_LOCK
Out
Notes:
1. These are test signals for factory use only and must be pulled up to OV for normal processor operation.
DD
2
2. For I C or JTAG operation, the TCK and TDI signals must be pulled down to ground with a 10 kΩ resistor. See Section 3.10.3 on
page 43.
3. Bus ratios 8:1 and 16:1 are not supported for PI Input functionality.
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.
5. This signal should not be connected.
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point
immediately behind the module. They should not be connected to GND and V planes.
DD
7. BiDi = bidirectional. OD = open drain.
8. Using the 4:1 or 12:1 ratio with multiplier of 12 limits the use of power tuning to (frequency)/2.
9. The PLL_MULT and PLL_RANGE(1:0) bits can be overwritten by JTAG commands and the BUS_CFG bits can be changed by
SCOM commands during the POR sequence. See the PowerPC 970FX Power On Reset Application Note for more details
10. Must be pulled down with a 10 kΩ resistor to GND.
11. The TRST signal must be pulled up to OV with a 10 kΩ resistor.
DD
System Design Information
Page 72 of 78
Version 2.5
March 26, 2007
IBM [ IBM ]
