欢迎访问ic37.com |
会员登录 免费注册
发布采购

IBM25PPC970FX6UB186ET 参数 Datasheet PDF下载

IBM25PPC970FX6UB186ET图片预览
型号: IBM25PPC970FX6UB186ET
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 64-Bit, 1600MHz, CMOS, CBGA576, 25 X 25 MM, 1 MM PITCH, CERAMIC, BGA-576]
分类和应用: 时钟外围集成电路
文件页数/大小: 78 页 / 3525 K
品牌: IBM [ IBM ]
 浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第67页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第68页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第69页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第70页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第72页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第73页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第74页浏览型号IBM25PPC970FX6UB186ET的Datasheet PDF文件第75页  
Datasheet  
PowerPC 970FX RISC Microprocessor  
5.7 Input-Output Use  
This section provides information about the PowerPC 970FX input and output signals and their use.  
5.7.1 Chip Signal I/O and Test Pins  
Table 5-8 shows the system signal names, debug, and test pins. There are 172 total chip pads. These  
include three power/capacitance pins.  
Table 5-8. Input/Output Signal Descriptions (Page 1 of 4)  
Pin Name  
Width  
44  
In/Out  
In  
System/Debug Function  
Notes  
System: Processor interface (PI) address or data and control informa-  
tion.  
ADIN(0:43)  
ADOUT(0:43)  
AFN  
44  
1
Out  
Out  
System: PI address or data and control information out.  
Pin AFN is a spare output pin.  
Analog ground.  
5
ANALOG_GND  
ATTENTION  
1
1
1
Out  
In  
Debug: signal from PowerPC 970FX.  
Analog power supply.  
AV  
1
DD  
AVP_RESET  
BI_MODE  
1
In  
For manufacturing test use only.  
Dedicated manufacturing signal.  
1
In  
1
Bus configuration select. These signals select the bus frequency divi-  
sion ratio from the processor clock to the bus speed.  
‘000’  
‘001’  
‘010’  
‘011’  
‘100’  
‘101’  
‘110’  
‘111’  
2:1  
3:1  
4:1  
BUS_CFG(0:2)  
3
In  
3, 8  
6:1  
8:1  
12:1  
16:1  
Not valid  
BYPASS  
1
1
In  
In  
This signal is used to bypass the PLL.  
1
Debug: adjusts the C1 clock to internal latches and is not used for  
normal operation.  
C1_UND_GLOBAL  
Notes:  
10  
1. These are test signals for factory use only and must be pulled up to OV for normal processor operation.  
DD  
2
2. For I C or JTAG operation, the TCK and TDI signals must be pulled down to ground with a 10 kΩ resistor. See Section 3.10.3 on  
page 43.  
3. Bus ratios 8:1 and 16:1 are not supported for PI Input functionality.  
4. These are test signals for factory use only and must be pulled down to GND for normal processor operation.  
5. This signal should not be connected.  
6. These pins can be used to measure on-chip voltage drop and noise. They should be connected to a backside probe point  
immediately behind the module. They should not be connected to GND and V planes.  
DD  
7. BiDi = bidirectional. OD = open drain.  
8. Using the 4:1 or 12:1 ratio with multiplier of 12 limits the use of power tuning to (frequency)/2.  
9. The PLL_MULT and PLL_RANGE(1:0) bits can be overwritten by JTAG commands and the BUS_CFG bits can be changed by  
SCOM commands during the POR sequence. See the PowerPC 970FX Power On Reset Application Note for more details  
10. Must be pulled down with a 10 kΩ resistor to GND.  
11. The TRST signal must be pulled up to OV with a 10 kΩ resistor.  
DD  
Version 2.5  
System Design Information  
Page 71 of 78  
March 26, 2007