Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
5.3 PLL Power Supply Filtering
The 750GX microprocessor has two separate AVDD signals (A1VDD and A2VDD), which provide power to the
clock generation PLL.
Most designs are expected to use a single PLL configuration mode throughout the application. These types of
designs should use the default PLL (PLL0), filtering its respective supply, A1VDD. The A2VDD supply signal
should be grounded through a 100 Ω resistor, as shown in Figure 5-1 on page 51.
For designs planning to optimize power savings through dynamic switching between dual PLL circuits, it is
recommended, though not required, that each AVDD have a separate voltage input and filter circuit. This
optional circuit is also shown.
To ensure stability of the internal clock, the power supplied to the AVDD input signals should be filtered using
a circuit similar to the one shown in Figure 5-1 on page 51. The circuit should be placed as close as possible
to the AVDD pin to ensure it filters out as much noise as possible.
For descriptions of the sample PLL power supply filtering circuits, see Table 5-3.
Table 5-3. Sample PLL Power Supply Filtering Circuits
Number of
Filtering
Circuits
Ferrite
Beads
Recommended
Circuit Design
Circuit Description
Circuit Figure
Notes
Single PLL circuit configuration that uses the A1V
DD
1
1
2
1
1
2
Figure 5-1 on page 51
Figure 5-2 on page 51
Figure 5-3 on page 52
Yes
Optional
Yes
1, 2
1, 2
2, 3
and ties the A2V pin to GND.
DD
Single PLL circuit configuration that uses both the
A1V and the A2V pins and a single ferrite bead.
DD
DD
Dual PLL configuration that uses a separate circuit
for the A1V pin and for the A2V pin.
DD
DD
Notes:
1. Optional configurations are supported, though not recommended.
2. This circuit design can be used with the dual PLL feature enabled, though optimum power savings may not be realized.
For additional information, see Figure 5-3, Dual PLL Power Supply Filter Circuits, on page 52.
3. This circuit design can be used with the dual PLL feature enabled to optimize power savings.
System Design Information
Page 50 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
