Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
Table 5-2. 750GX Microprocessor PLL Configuration (Continued)
Frequency Range Supported by VCO Having an Example Range of...
PLL_CFG [0:4]
Processor to Bus
Frequency Ratio
(PTBFR)
1
SYSCLK (MHz)
Core (MHz)
Minimum
Maximum
Minimum
Maximum
Binary
Decimal
(SYSCLK
)
(SYSCLKMAX
154
143
133
125
118
111
105
100
91
)
(Core FrequencyMIN
)
(Core FrequencyMAX)
MIN
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Notes:
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
6.5×
7×
77
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
500
N/A
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
N/A
71
7.5×
8×
67
62
8.5×
9×
59
55
9.5×
10×
11×
12×
13×
14×
15×
16×
17×
18×
19×
20×
51
50
45
42
83
38
77
36
71
33
66
31
63
29
59
28
56
26
53
25
50
2
Off
N/A
N/A
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
2. In clock-off mode, no clocking occurs inside the 750GX regardless of the SYSCLK input.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. The 2×–3.5× processor-to-bus ratios are currently not supported when miss-under-miss is enabled (HID0(14) = '1').
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 49 of 73
IBM [ IBM ]
