Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
High-frequency decoupling capacitors should be located as close as possible to the processor with low lead
inductance to the ground and voltage planes.
Decoupling capacitors are recommended on the back of the card, directly opposite the module. The recom-
mended placement and number of decoupling capacitors, 34 VDD-GND capacitors and 44 OVDD-GND
capacitors, are described in Figure 5-4 on page 54. The recommended decoupling capacitor specifications
are provided in Table 5-4. The placement and usage described here are guidelines for decoupling capacitors
and should be applied for system designs.
Table 5-4. Recommended Decoupling Capacitor Specifications
Item
Description
Type X5R or Y5V
10 V minimum
0402 size
Decoupling capacitor specifications:
40 × 20 mils, nominally
1.0 mm × 0.5 mm 0.1 mm on both dimensions
100 nF
34 V -GND capacitors
Recommended minimum number of decou-
pling capacitors on the back of the card:
DD
44 OV -GND capacitors
DD
Note: The decoupling capacitor electrodes are located directly opposite their corresponding BGA pins where
possible. Also, each electrode for each decoupling capacitor needs to be connected to one or more BGA pins
(balls) with a short electrical path. Thus, through-vias adjacent to the decoupling capacitors are recom-
mended.
The card designer can expand on the decoupling capacitor recommendations by doing the following:
• Adding additional decoupling capacitors.
If using additional decoupling capacitors, verify that these additional capacitors do not reduce the number
of card vias or cause the vias to lose proximity to each capacitor electrode.
• Adding additional through-vias or blind-vias.
Card technologies are available that will reduce the inductance between the decoupling capacitor and the
BGA pin (ball). Replacing single vias with multiple vias is certainly approved. Place GND vias close to
VDD or OVDD vias to reduce loop inductance.
Figure 5-4 on page 54 shows the mapping of Power, Ground, and Signal pin assignments, and recom-
mended layout of decoupling capacitors under application conditions. In test mode, pins C11 and G8 can be
used as Kelvin probes, in which case the pins should be disconnected from card GND and VDD. Capacitors
should not be connected to the Kelvin pins during Kelvin probe voltage measurements.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 53 of 73
IBM [ IBM ]
