Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
The following sequence can be used to change processor clock frequency.
Note: Assume PLL0 is currently the source for the processor clock.
1. Configure PLL1 to produce the desired clock frequency by setting HID1[PR1] and HID1[PC1] to the
appropriate values.
2. Wait for PLL1 to lock. The lock time is the same for both PLLs (see Table 3-7, Clock AC Timing Specifica-
tions, on page 18).
3. Set HID1[PS] to '1' to initiate the transition from PLL0 to PLL1 as the source of the processor clocks.
From the time the HID1 register is updated to select the new PLL, the transition to the new clock fre-
quency will complete within three bus cycles. After the transition, the HID(PSS) bit indicates which PLL is
in use.
After both PLLs are running and locked, the processor frequency can be toggled with very low latency.
For example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock.
HID1[PS] can be reset to '0', causing the processor clock source to transition from PLL1 back to PLL0. If
PLL0 will not be needed for some time, it can be configured to be off while not in use. This is done by
resetting the HID1[PC0] field to '0', and setting HID1[PI0] to '1'. Turning the non-selected PLL off results
in a modest power savings, but introduces added latency when changing frequency. If PLL0 is configured
to be off, the procedure for switching to PLL0 as the selected PLL involves changing the configuration
and range bits, waiting for lock, and then selecting PLL0, as described in the previous paragraph.
5.2.2 Restrictions and Considerations for PLL Configuration
Consider the following when reconfiguring the PLLs:
• The configuration and range bits in HID1 should only be modified for the non-selected PLL, since it will
require time to lock before it can be used as the source for the processor clock.
• The HID1[PI0] bit should only be modified when PLL0 is not selected.
• Whenever one of the PLLs is reconfigured, it must not be selected as the active PLL until enough time
has elapsed for the PLL to lock.
• At all times, the frequency of the processor clock, as determined by the various configuration settings,
must be within the specification range for the current operating conditions.
• Never select a PLL that is in the off configuration.
5.2.2.1 Configuration Restriction on Frequency Transitions
It is considered a programming error to switch from one PLL to the other when both are configured in a
half-cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (PC0) and PLL1 configured in
13:2 mode (PC1), changing the select bit (HID1[PS]) is not allowed. In cases where such a pairing of configu-
rations is desired, an intermediate full-cycle configuration must be used between the two half-cycle modes.
For example, with PLL0 at 9:2, PLL1, configured at 6:1, is selected. Then PLL0 is reconfigured at 13:2,
locked, and selected.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 47 of 73
IBM [ IBM ]
