Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
5. System Design Information
This section provides electrical and thermal design recommendations for successful applications on the
750GX.
5.1 Core Voltage Operation
The 750GX supports a single VDD setting for a specific application condition. The AVDD supplies can be set to
the same voltage as VDD, and the PLL range (PLL_RNG[0:1]) bits are as defined in Table 5-1 on page 48.
5.2 Low Voltage Operation at Lower Frequency
Due to the relationship of power to frequency and voltage (power proportional to frequency and a square of
voltage), running the processor at an associated lower voltage and lower frequency results in significant
power savings. Low voltage application conditions will be defined after characterization is completed.
After the 750GX application condition, within the supported limits, has been selected, the 750GX’s dual PLL
feature can also be used to provide additional power savings.
5.2.1 Overview
The 750GX design includes two PLLs (PLL0 and PLL1), allowing the processor clock frequency to dynami-
cally change between the PLL frequencies via software control. Use the bits in Hardware Implementation
Dependent Register 1 (HID1) to specify:
• The frequency range of each PLL
• The clock multiplier for each PLL
• External or internal control of PLL0
• Which PLL is selected (which is the source of the processor clock at any given time)
At power-on reset, the HID1 register contains zeros for all the non-read-only bits (bits 7 to 31). This configura-
tion corresponds to the selection of PLL0 as the source of the processor clocks and selects the external
configuration and range pins to control PLL0. The external configuration and range pin values are accessible
to software using HID1 read-only bits 0-6. PLL1 is always controlled by its internal configuration and range
bits. The HID1 setting associated with hard reset corresponds to a PLL1 configuration of clock off, and selec-
tion of the medium frequency range.
As stated in the hardware specification, HRESET must be asserted during power up long enough for the
PLL(s) to lock, and for the internal hardware to be reset. Once this timing is satisfied, HRESET can be
negated. The processor now will proceed to execute instructions, clocked by PLL0 as configured via the
external pins. The processor clock frequency can be modified from this initial setting in one of two ways. First,
as with earlier designs, HRESET can be asserted, and the external configuration pins can be set to a new
value. The machine state is lost in this process, and, as always, HRESET must be held asserted while the
PLL relocks, and the internal state is reset. Second, the introduction of another PLL provides an alternative
means of changing the processor clock frequency, which does not involve the loss of machine state nor a
delay for PLL relock.
System Design Information
Page 46 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
