Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
5.2.3 PLL_RNG[0:1] Definitions for Dual PLL Operation
The dual PLLs on the 750GX are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given
SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and voltage controlled oscillator
(VCO) frequency of operation. The 750GX PLL range configuration for dual PLL operation is shown in the
following table.
Table 5-1. PLL_RNG[0:1] Definitions for Dual PLL Operation
PLL_RNG[0:1]
00 (default)
01 (fast)
PLL Frequency Range
600 MHz–900 MHz
900 MHz–1.0 GHz
500 MHz–600 MHz
Reserved
10 (slow)
11 (reserved)
Note: PLL_RNG bit settings are valid for a V range of 1.4 V–1.55 V and a temperature range of -40°C–105°C.
DD
5.2.4 PLL Configuration
Table 5-2 shows the PLL configuration for the 750GX for nominal frequencies.
Table 5-2. 750GX Microprocessor PLL Configuration
Frequency Range Supported by VCO Having an Example Range of...
PLL_CFG [0:4]
Processor to Bus
Frequency Ratio
(PTBFR)
1
SYSCLK (MHz)
Core (MHz)
Minimum
Maximum
(SYSCLKMAX
Minimum
Maximum
Binary
Decimal
)
(Core FrequencyMIN
)
(Core FrequencyMAX)
(SYSCLK
N/A
N/A
N/A
N/A
N/A
200
167
143
125
111
100
91
)
MIN
2
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
Notes:
0
1
Off
N/A
Off
Off
Off
Off
2
Off
N/A
3
2
PLL Bypass
N/A
N/A
N/A
N/A
500
500
500
500
500
500
500
500
N/A
N/A
N/A
500
600
700
800
900
1000
1000
1000
3
3
PLL Bypass
N/A
4
4
2×
N/A
4
5
2.5×
200
4
6
3×
200
4
7
3.5×
200
8
4×
4.5×
5×
200
9
200
10
11
12
200
5.5×
6×
182
83
166
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
2. In clock-off mode, no clocking occurs inside the 750GX regardless of the SYSCLK input.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. The 2×–3.5× processor-to-bus ratios are currently not supported when miss-under-miss is enabled (HID0(14) = '1').
System Design Information
Page 48 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
