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IBM25PPC750GXECB5H83T 参数 Datasheet PDF下载

IBM25PPC750GXECB5H83T图片预览
型号: IBM25PPC750GXECB5H83T
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 933MHz, CMOS, CBGA292, 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292]
分类和应用: 时钟外围集成电路
文件页数/大小: 74 页 / 1054 K
品牌: IBM [ IBM ]
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Datasheet  
IBM PowerPC 750GX RISC Microprocessor  
DD1.X  
3.6 60x Bus Output AC Specifications  
Table 3-9 provides the 60× bus output AC timing specifications for the 750GX as defined in Figure 3-7 on  
page 25.  
Table 3-9. 60x Bus Output AC Timing Specifications  
See Table 3-2 on page 15 for operating conditions.1, 4, 6  
Figure 3-7  
Timing  
Reference  
1.8 V  
Min.  
2.5 V  
Min.  
3.3 V  
Min.  
Characteristic  
Unit  
ns  
Notes  
Max.  
Max.  
Max.  
SYSCLK to Output Driven  
(Output Enable Time)  
12  
0.3  
0.3  
0.3  
13  
14  
SYSCLK to Output Valid  
2.4  
2.3  
2.4  
ns  
ns  
5
SYSCLK to Output Invalid (Output Hold)  
1.0  
0.6  
0.6  
SYSCLK to Output High Impedance  
(all signals except address retry [ARTRY],  
address bus busy [ABB], and data bus  
busy [DBB])  
15  
2.5  
2.5  
2.5  
ns  
SYSCLK to ABB and DBB high impedance  
after precharge  
16  
17  
1.0  
3.0  
1.0  
3.0  
1.0  
3.0  
t
2
3
SYSCLK  
SYSCLK to ARTRY high impedance  
before precharge  
ns  
0.2 ×  
SYSCLK  
0.2 ×  
SYSCLK  
0.2 ×  
SYSCLK  
18  
SYSCLK to ARTRY precharge enable  
t
+
t
+
t
+
ns  
1.0  
1.0  
1.0  
19  
20  
Maximum delay to ARTRY precharge  
1.0  
2.0  
1.0  
2.0  
1.0  
2.0  
t
t
2, 3  
2, 3  
SYSCLK  
SYSCLK to ARTRY high impedance  
after precharge  
SYSCLK  
Notes:  
1. All output specifications are measured from the V of the rising edge of SYSCLK to the midpoint of the output signal in question  
M
using a test load as shown in Figure 3-6 on page 24. Both input and output timings are measured at the pin. Timings are deter-  
mined by design.  
2. t  
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied  
SYSCLK  
by the period of SYSCLK to compute the actual time duration of the parameter in question.  
3. Nominal precharge width for ARTRY is 1.0 t  
.
SYSCLK  
4. Guaranteed by design and characterization, and not tested.  
5. Output Valid timing increases as the V is reduced. These values assume a V minimum of 1.4 V.  
DD  
DD  
6. See Figure 3-6 on page 24 and Figure 3-7 on page 25 for output loading and timing definitions.  
750GX_ds_body.fm SA14-2765-02  
September 2, 2005  
Electrical and Thermal Characteristics  
Page 23 of 73  
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