Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
3.6.1 IEEE 1149.1 AC Timing Specifications
Table 3-10 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in the following figures:
To find out more about...
JTAG Clock Input Timing Diagram
See...
Figure 3-8 on page 27.
Figure 3-9 on page 27.
Figure 3-10 on page 27.
Figure 3-11 on page 28.
TRST Timing Diagram
Boundary-Scan Timing Diagram
Test Access Port Timing Diagram
The five JTAG signals are: test data input (TDI), test data output (TDO), test mode select (TMS), test clock
(TCK), and test reset (TRST).
Table 3-10. JTAG AC Timing Specifications (Independent of SYSCLK)
See Table 3-2 on page 15 for operating conditions.
Figures 3-8
through 3-11
Characteristic
Min.
Max.
Unit
Notes
Timing
Reference
TCK frequency of operation
TCK cycle time
0
40
15
0
25
—
—
2
MHz
ns
ns
ns
—
1
2
TCK clock pulse width measured at 1.1 V
TCK rise and fall times
3
4
4
Specification obsolete, intentionally omitted
TRST assert time
—
25
0
—
—
—
—
8
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
6
Boundary-scan input data setup time
Boundary-scan input data hold time
TCK to output data valid
7
13
—
3
2
8
3, 5
3, 4
9
TCK to output high impedance
TMS, TDI data setup time
19
—
—
12
9
10
11
12
13
14
0
TMS, TDI data hold time
15
2.0
3
TCK to TDO data valid
5
4
TCK to TDO high impedance
TCK to output data invalid (output hold)
0
—
Notes:
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.
2. Non-JTAG signal input timing with respect to TCK.
3. Non-JTAG signal output timing with respect to TCK.
4. Guaranteed by characterization and not tested.
5. Minimum specification guaranteed by characterization and not tested.
Electrical and Thermal Characteristics
Page 26 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
