Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
3.4 Spread Spectrum Clock Generator
3.4.1 Design Considerations
When designing with the Spread Spectrum Clock Generator (SSCG), there are a number of design issues
that must be taken into account.
SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750GX to operate in
this environment, it must be able to accurately track the SSCG clock jitter.
The accuracy to which the 750GX PLL can track the SSCG clock is referred to as tracking skew. When
performing system timing analysis, the tracking skew must be added or subtracted to the I/O timing specifica-
tions because the tracking skew appears as a static phase error between the internal PLL and the SSCG
clock.
To minimize the impact on I/O timings, the following SSCG configuration is recommended:
• Down spread mode, less than or equal to 1% of the maximum frequency.
• A modulation frequency of 30 kHz.
• Linear sweep modulation or “Hershey’s Kiss” (as in a Lexmark1 profile) modulation profile as shown in
Figure 3-2.
In this configuration, the tracking skew is less than 100 ps.
Figure 3-2. Linear Sweep Modulation Profile
0%
Down spread
frequency
change
-1%
0 µs
33.3 µs
Time Increases
1. See patent 5,631,920.
750GX_ds_body.fm SA14-2765-02
September 2, 2005
Electrical and Thermal Characteristics
Page 19 of 73
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