Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
3.5 60x Bus Input AC Specifications
Table 3-8 provides the 60x bus AC timing specifications defined in Figure 3-4 and Figure 3-5 on page 22.
Table 3-8. 60x Bus Input AC Timing Specifications
See Table 3-2 on page 15 for operating conditions.1, 5, 6
Figure 3-4
and 3-5
Timing
1.8 V Mode
2.5 V Mode
3.3 V Mode
Characteristic
Unit
ns
Notes
2, 3, 4
Min.
1.0
Max.
Min.
1.1
Max.
Min.
1.6
Max.
Reference
10a
10c
11a
11c
Input setup: SYSCLK to inputs valid.
—
—
—
4
—
—
—
4
—
—
—
4
Mode select input setup to HRESET (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
sysclk
cycles
8
0.45
0
8
0.3
0
8
0.3
0
Input hold: SYSCLK to inputs invalid
ns
HRESET to mode select input hold (TLBI-
SYNC, DRTRY, L2_TSTCLK, DBDIS,
QACK, and DBWO)
sysclk
cycles
2, 4
V
Measurement reference voltage for inputs
OV /2
—
V
M
DD
V
—
0.2
—
—
0.2
—
—
0.2
—
IL-AC
IH-AC
AC timing reference levels
7
V
OV
OV
OV
DD - 0.2
DD - 0.2
DD - 0.2
Slew Rate Reference input slew rate
1.0
—
1.5
—
2.0
—
V/ns
Notes:
1. Input specifications are measured from the midpoint voltage (V ) of the signal in question to the V of the rising edge of the input
M
M
SYSCLK. Timings are measured at the pin (see Figure 3-4 on page 21).
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-5 on page 22).
3. t is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the
SYSCLK
period of SYSCLK to compute the actual time duration (in ns) of the parameter in question.
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
bus clocks after the PLL relock time during the power-on reset sequence.
5. All values are guaranteed by design, and are not tested.
6. Refer to Section 3.5.1 on page 20 and Figure 3-3 on page 21 for input setup timing definitions.
7. Input reference signal levels used to establish the timings defined in this table.
3.5.1 Input Setup Timing
The information in this subsection is provided to clarify the criteria used to establish the timings in Table 3-8.
The DC Electrical Specifications shown in Table 3-4 on page 16 are not altered by this clarification. The valid
input signal levels remain VIH and VIL.
The input setup times shown as 10a in Table 3-8 specify the required time from the input signal crossing VM
to the rising edge of SYSCLK crossing VM.
For the timings in Table 3-8 to be valid, the falling edge of the input signal shown in Table 3-8 is assumed to
transition through VM and cross VIL-AC at the slew rate specified in Table 3-8. Input signals that do not reach
the VIL-AC boundary, or slew from VM to VIL-AC more slowly than specified, will result in longer input setup
times.
In the same way, on the rising edge, the input signal must continue past VM and cross the VIH-AC boundary
within the specified minimum slew rate. Input signals that do not reach the VIH-AC boundary within the slew
rate specified will result in longer input setup times.
Figure 3-4 provides the input timing diagram for the 750GX.
Electrical and Thermal Characteristics
Page 20 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
IBM [ IBM ]
