PowerPC 440GP Embedded Processor Data Sheet
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0
from the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However
MemClkOut0 is the same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the
specific application and requires a thorough understanding of the memory system in general (refer to
the DDR SDRAM controller chapter in the PowerPC 440GP User’s Manual).
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted,
and MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0
by 90° creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and
lengths. Values are calculated over best case and worst case processes with speed, temperature, and
voltage as follows:
Best Case = Fast process, -40°C, +1.9V
Worst Case = Slow process, +85°C, +1.7V
Note: In all the following DDR tables and timing diagrams, the maximum values are measured under worst
case conditions. The minimum values (best case) are estimates based on comparable timing in a similar chip
of a different technology.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
DDR SDRAM Signal Termination
MemClkOut0
10pF
120Ω
10pF
MemClkOut0
V
= V /2
DD
TT
PPC440GP
50Ω
Addr/Ctrl/Data/DQS
10pF
Page 61 of 72
5/13/04
IBM [ IBM ]
