PowerPC 440GP Embedded Processor Data Sheet
I/O Timing—DDR SDRAM T and T
SD
HD
Notes:
1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 133MHz.
3. The time values in the table include 1/4 of a cycle at 133MHz (7.5ns x 0.25 = 1.875 ns).
4. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and
add 1/4 of the cycle time for the lower clock frequency (e.g., TSD - 1.875 + 0.25TCYC).
TSD (ns)
THD (ns)
Signal Names
MemData00:07, DM0
MemData08:15, DM1
MemData16:23, DM2
MemData24:31, DM3
MemData32:39, DM4
MemData40:47, DM5
MemData48:55, DM6
MemData56:63, DM7
ECC0:7, DM8
Reference Signal
DQS0
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
1.375
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T ) is provided.
MD
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative
to the PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can
be programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the
value set in RDCT. The delay of Read Clock relative to the PLB clock (T ) shown below assumes the
RD
programmable Read Clock delay is set to zero.
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
T
MD
850ps
T
min =
MD
T
max =
2600ps
MD
Read Clock
T
RD
0ps
T
min =
RD
300ps
T
max =
RD
Page 65 of 72
5/13/04
IBM [ IBM ]
