PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 3 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
4. The clock frequency for SMII operation is 125MHz 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
System Interface
SysClk
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
7.1
n/a
n/a
7.1
TmrClk
async
async
async
async
async
SysReset
Halt
n/a
n/a
n/a
n/a
SysErr
n/a
n/a
n/a
n/a
10.3
n/a
TestEn
n/a
n/a
n/a
n/a
DrvrInh1:2
GPIO00:31
Trace Interface
TrcClk
n/a
10.3
10.3
10.3
10.3
10.3
7.1
7.1
7.1
7.1
TrcBS0:2
TrcES0:4
TrcTS0:6
Page 59 of 72
5/13/04
IBM [ IBM ]
