PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 2 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
4. The clock frequency for SMII operation is 125MHz 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
Ethernet RMII Interface
EMC0RxD0:1
EMC0RxErr
2
2
1
1
n/a
n/a
n/a
11
n/a
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
7.1
7.1
7.1
n/a
n/a
7.1
7.1
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMCTxClk
EMCRxClk
EMCRxClk
EMCRxClk
EMCTxClk
EMC0CrSDV
EMC0TxD0:1
EMC0:1TxEn
EMC1RxD0:1
EMC1RxErr
n/a
n/a
n/a
n/a
n/a
10.3
10.3
10.3
n/a
11
2
n/a
n/a
n/a
11
n/a
n/a
n/a
2
EMC1CrSDV
EMC1TxD0:1
EMCRefClk
n/a
n/a
n/a
n/a
n/a
10.3
10.3
n/a
n/a
3, async
Ethernet SMII Interface
EMC0:1RxD
0.8
n/a
0.8
n/a
n/a
6.2
na/
2
10.3
10.3
7.1
7.1
EMCRxClk
EMCTxClk
EMC0:1TxD
Internal Peripheral Interface
IICxSClk
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
15.3
15.3
n/a
10.2
10.2
n/a
n/a
7.1
n/a
n/a
n/a
7.1
n/a
7.1
n/a
7.1
n/a
7.1
IICxSDA
UARTSerClk
UART0_Rx
UART0_Tx
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RI
UART0_RTS
UART1_Rx
UART1_Tx
UART1_DSR/CTS
UART1_RTS/DTR
Interrupts Interface
IRQ00:12
n/a
n/a
n/a
n/a
n/a
10.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
n/a
10.3
n/a
10.3
n/a
n/a
JTAG Interface
TDI
n/a
n/a
n/a
n/a
async
async
async
async
async
TMS
TDO
15.3
n/a
10.2
n/a
TCK
TRST
n/a
n/a
Page 58 of 72
5/13/04
IBM [ IBM ]
