PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—400, 466, and 500MHz
Notes:
1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
External Slave Peripheral Interface
PerData00:31
PerAddr00:31
PerPar0:3
3
1
1
9
7.6
8.4
6.5
6
0
0
15.3
15.3
15.3
15.3
15.3
15.3
15.3
15.3
n/a
10.2
10.2
10.2
10.2
10.2
10.2
10.2
10.2
n/a
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
3
4
1
0
PerWBE0:3
PerCS0:7
2.5
n/a
n/a
n/a
2.5
5
1
0
n/a
n/a
n/a
1
0
PerOE
6
0
PerWE
7
0
PerBLast
5
n/a
n/a
n/a
n/a
0
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerReady[RcvrInh]
PerR/W
1
n/a
5.6
n/a
7
2.5
dc
n/a
dc
1
15.3
n/a
10.2
n/a
DMAReq0:3
DMAAck0:3
EOT0:3/TC0:3
dc
n/a
dc
15.3
15.3
10.2
10.2
6.8
0
External Master Peripheral Interface
PerClk
n/a
n/a
3.5
n/a
2.5
n/a
n/a
4.5
n/a
n/a
1
n/a
6.2
n/a
6.4
n/a
6.2
6.2
n/a
n/a
0
15.3
15.3
n/a
10.2
10.2
n/a
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
1
ExtReset
HoldReq
HoldAck
ExtReq
ExtAck
n/a
0
n/a
1
15.3
n/a
10.2
n/a
n/a
0
n/a
n/a
1
15.3
15.3
15.3
10.2
10.2
10.2
BusReq
PerErr
0
n/a
Page 60 of 72
5/13/04
IBM [ IBM ]
