PowerPC 440GP Embedded Processor Data Sheet
I/O Specifications—All Speeds (Part 1 of 3)
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz
and 1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
3. The clock frequency for RMII operation is 50MHz 100ppm.
4. The clock frequency for SMII operation is 125MHz 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
Input (ns)
Output (ns)
Output Current (mA)
I/O H I/O L
(minimum) (minimum)
Signal
Clock
Notes
Setup Time Hold Time Valid Delay
Hold Time
(TOH min)
(TIS min)
(TIH min)
(TOV max)
PCI-X Interface
PCIXAD00:63
PCIXC3:0[BE3:0]
PCIXParLow
PCIParHigh
PCIXFrame
PCIXINT
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
n/a
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
n/a
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
dc
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
dc
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
n/a
0.5
0.5
n/a
n/a
0.5
0.5
n/a
0.5
n/a
n/a
0.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
n/a
1.5
1.5
n/a
n/a
1.5
1.5
n/a
1.5
n/a
n/a
1.5
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
2
2
2
2
2
async
PCIXIRDY
Note 2 (3)
Note 2 (3)
Note 2 (3
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
dc
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
dc
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
n/a
2
PCIXTRDY
PCIXStop
2
2
PCIXDevSel
PCIXIDSel
PCIXPErr
2
2
2
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
n/a
PCIXSErr
2
PCIXClk
async
PCIXReset
PCIXReq64
PCIXAck64
PCIXCap
n/a
n/a
n/a
n/a
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
Note 2 (3)
Note 2 (3)
Note 2 (3)
0.5 (0)
0.5 (0)
0.5 (0)
3.8 (6)
3.8 (6)
n/a
0.7 (Note 2)
0.7 (Note 2)
n/a
2
2
2
2
2
2
2
PCIX133Cap
PCIXM66En
PCIXReq0:5
PCIXGnt0:5
Ethernet MII Interface
EMCRxD0:3
EMCRxDV
EMCRxClk
EMCRxErr
EMCTxD0:3
EMCTxEn
3.8
0.7
Note 2 (3)
Note 2 (3)
n/a)
0.5 (0)
0.5 (0)
n/a
n/a
n/a
n/a
n/a
3.8 (6)
0.7 (Note 2)
4
1
n/a
n/a
n/a
n/a
15
n/a
n/a
n/a
n/a
2
n/a
n/a
n/a
n/a
n/a
n/a
7.1
7.1
n/a
7.1
n/a
n/a
7.1
7.1
EMCRxClk
EMCRxClk
1
4
1
1
n/a
4
n/a
1
n/a
1, async
n/a
EMCRxClk
EMCTxClk
EMCTxClk
1
n/a
n/a
n/a
n/a
n/a
n/a
n/a
n/a
10.3
10.3
n/a
1
1
15
2
EMCTxClk
EMCTxErr
n/a
15
n/a
2
1, async
1
10.3
n/a
EMCTxClk
EMCMDClk
EMCCrS
n/a
n/a
n/a
n/a
1, async
1, async
1
EMCCD
n/a
EMCMDIO
EMCMDClk
10.3
10.3
n/a
n/a
n/a
n/a
1, async
Page 57 of 72
5/13/04
IBM [ IBM ]
