Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description (Part 6 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
Trace Interface
[TS1E]
[TS2E]
Even Trace execution status. To access this function, software
must toggle a DCR bit
5V tolerant
3.3V LVTTL
O
O
O
1
1
1
[TS1O]
[TS2O]
Odd Trace execution status. To access this function, software
must toggle a DCR bit
5V tolerant
3.3V LVTTL
Trace status. To access this function, software must toggle a
DCR bit
5V tolerant
3.3V LVTTL
[TS3:6]
Trace interface clock. Operates at half the CPU core frequency.
To access this function, software must toggle a DCR bit
5V tolerant
3.3V LVTTL
[TrcClk]
O
1
Note: Initialization strapping must hold this pin low (0) during
reset.
Power
Ground
GND
na
na
na
Note: K10-K14, L10-L14, M10-M14, N10-N14, and P10-P14 are
also thermal balls.
OV
Output driver voltage—3.3V.
Logic voltage—1.8V.
na
na
na
na
na
na
DD
V
DD
Other pins
Reserved pins. Do not make voltage, ground, or signal
connections to these pins.
Reserved
na
na
na
Page 38 of 52
6/9/03
IBM [ IBM ]
