Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description (Part 5 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
JTAG Interface
5V tolerant
3.3V LVTTL
TDI
TMS
TDO
TCK
Test data in.
I
I
1, 4
1, 4
5V tolerant
3.3V LVTTL
JTAG test mode select.
Test data out.
5V tolerant
3.3V LVTTL
O
I
JTAG test clock. The frequency of this input can range from DC to
25MHz.
5V tolerant
3.3V LVTTL
1, 4
5
JTAG reset. TRST must be low at power-on to initialize the JTAG
controller and for normal operation of the PPC405EP.
5V tolerant
3.3V LVTTL
TRST
I
System Interface
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. Implemented as an open-
drain output (two states; 0 or open circuit).
5V tolerant
3.3V LVTTL
SysReset
I/O
1, 2
5V tolerant
3.3V LVTTL
SysErr
Halt
Set to 1 when a Machine Check is generated.
Halt from external debugger.
O
I
6
1, 2
1
5V tolerant
3.3V LVTTL
General Purpose I/O. All of the GPIO signals are multiplexed with
other signals.
5V tolerant
3.3V LVTTL
GPIO00:31
I/O
Test Enable. Used only for manufacturing tests. Pull down for
normal operation.
1.8V CMOS
w/pull-down
TestEn
SysClk
I
I
I
Main system clock input.
3.3V LVTTL
5V tolerant
3.3V LVTTL
[RejectPkt0:1]
External request to reject a packet.
AV
Clean voltage input for the PLL.
Clean Ground input for the PLL.
I
I
DD
AGND
Page 37 of 52
6/9/03
IBM [ IBM ]
