Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description (Part 3 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
I/O
O
Type
Notes
SDRAM Interface
Memory data bus.
Notes:
MemData00:31
MemAddr12:00
3.3V LVTTL
3.3V LVTTL
1. MemData00 is the most significant bit (msb).
2. MemData31 is the least significant bit (lsb).
Memory address bus.
Notes:
1. MemAddr12 is the most significant bit (msb).
2. MemAddr00 is the least significant bit (lsb).
BA1:0
RAS
Bank Address supporting up to 4 internal banks.
Row Address Strobe.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
CAS
Column Address Strobe.
DQM for byte lane: 0 (MemData00:7),
1 (MemData08:15),
DQM0:3
O
3.3V LVTTL
2 (MemData16:23), and
3 (MemData24:31)
BankSel0:1
WE
Select up to two external SDRAM banks.
Write Enable.
O
O
O
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
ClkEn0:1
SDRAM Clock Enable.
Two copies of an SDRAM clock allows, in some cases, glueless
SDRAM attach without requiring this signal to be repowered by a
PLL or zero-delay buffer.
MemClkOut0:1
O
3.3V LVTTL
External Slave Peripheral Interface
Peripheral data bus.
5V tolerant
3.3V LVTTL
PerData00:15
I/O
I/O
1
1
Note: PerData00 is the most significant bit (msb) on this bus.
Peripheral address bus.
PerAddr03:05
PerAddr06:31
5V tolerant
3.3V LVTTL
Note: PerAddr03 is the most significant bit (msb) on this bus.
These pins act as byte-enables which are valid for an entire cycle
or as write-byte-enables which are valid for each byte on each
data transfer, allowing partial word transactions.
5V tolerant
3.3V LVTTL
PerWBE0:1
[PerWE]
O
O
7
Peripheral write enable. Low when either of the two PerWBE0:1
write byte enables are low.
5V tolerant
3.3V LVTTL
To access this function, software must toggle a DCR bit.
5V tolerant
3.3V LVTTL
PerCS0
Peripheral chip select bank 0.
O
O
7
Four additional peripheral chip selects
5V tolerant
3.3V LVTTL
[PerCS1:4]
1, 7
To access this function, software must toggle a DCR bit.
Page 35 of 52
6/9/03
IBM [ IBM ]
