Preliminary
PowerPC 405EP Embedded Processor Data Sheet
Signal Functional Description (Part 2 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 31 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 32.
Signal Name
Description
I/O
Type
Notes
5V tolerant
3.3V PCI
PCIReq1:2
PCIReq input when internal arbiter is used.
I
Gnt0 when internal arbiter is used
or
5V tolerant
3.3V PCI
PCIGnt0/Req
O
O
Req when external arbiter is used.
5V tolerant
3.3V PCI
PCIGnt1:2
Ethernet Interface
PHY0Rx0:1D3:0
PCIGnt output when internal arbiter is used.
Received data. This is a nibble wide bus from the PHY. The data
is synchronous with the PHY0RxClk.
5V tolerant
3.3V LVTTL
I
O
I
1
Transmit data. A nibble wide data bus towards the net. The data
is synchronous to the PHY0TxClk.
5V tolerant
3.3V LVTTL
EMC0Tx0:1D3:0
PHY0Rx0:1Err
PHY0Rx0:1Clk
Receive Error. This signal comes from the PHY and is
synchronous to the PHY0RxClk.
5V tolerant
3.3V LVTTL
1
1
5V tolerant
3.3V LVTTL
Receive Medium clock. This signal is generated by the PHY.
I
Receive Data Valid. Data on the Data Bus is valid when this
signal is activated. Deassertion of this signal indicates end of the
frame reception.
5V tolerant
3.3V LVTTL
PHY0Rx0:1DV
PHY0CrS0:1
I
I
1
1
Carrier Sense signal from the PHY. This is an asynchronous
signal.
5V tolerant
3.3V LVTTL
Transmit Error. This signal is generated by the Ethernet
controller, is connected to the PHY and is synchronous with the
PHYTxClk. It informs the PHY that an error was detected.
5V tolerant
3.3V LVTTL
EMC0Tx0:1Err
O
Transmit Enable. This signal is driven by the EMAC to the PHY.
Data is valid during the active state of this signal. Deassertion of
this signal indicates end of frame transmission. This signal is
synchronous to the PHY0TxClk.
5V tolerant
3.3V LVTTL
EMC0Tx0:1En
O
This clock comes from the PHY and is the Medium Transmit
clock.
5V tolerant
3.3V LVTTL
PHY0Tx0:1Clk
PHY0Col0:1
I
I
1
1
5V tolerant
3.3V LVTTL
Collision signal from the PHY. This is an asynchronous signal.
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with
respect to this clock.
5V tolerant
3.3V LVTTL
EMC0MDClk
EMC0MDIO
O
Management Data Input/Output is a bidirectional signal between
the Ethernet controller and the PHY. It is used to transfer control
and status information.
5V tolerant
3.3V LVTTL
I/O
1
Page 34 of 52
6/9/03
IBM [ IBM ]
