Table 14: Pinout Listing for the 255 CBGA Package (Continued)
Signal Name
TEA
Pin Number
Active
I/O
H13
Low
Low
High
Low
Low
High
High
Low
—
Input
Input
Input
Input
I/O
TLBISYNC
TMS
C04
B11
TRST
C10
TS
J13
TSIZ0-TSIZ2
TT0-TT4
WT
A13, D10, B12,
Output
I/O
B13, A15, B16, C14, C15
D02
Output
—
2
F06, F08, F09, F11, G07, G10, H06, H08,
H09, H11, J06, J08, J09, J11, K07, K10,
L06, L08, L09, L11
VDD
3
F03
Low
Output
VOLTDET
Note:
1. These are test signals for factory use only and must be pulled up to OVdd for normal operation.
2. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
3. Internally tied to GND in the 255 CBGA package to indicate to the power supply that a low-voltage pro-
cessor is present. This is NOT a supply pin.
PPC740 and PPC750 Hardware Specifications
24 of 44
Preliminary and subject to change without notice
IBM [ IBM ]
