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IBM25EMPPC750DBUB2660 参数 Datasheet PDF下载

IBM25EMPPC750DBUB2660图片预览
型号: IBM25EMPPC750DBUB2660
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 44 页 / 514 K
品牌: IBM [ IBM ]
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3.1.3 IEEE 1149.1 AC Timing Specifications  
Table 13 provides th e IEEE 1149.1 (J TAG) AC tim in g specification s as defin ed  
in Figu re 9 , Figu re 10 , Figu re 11 , an d Figu re 12 . Th e five J TAG sign als are;  
TDI, TDO, TMS, TCK, an d TRST.  
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK)  
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions" CL = 50 pF  
Num  
Characteristic  
Min  
Max  
Unit  
Notes  
TCK frequency of operation  
TCK cycle time  
0
33.3  
MHz  
ns  
1
30  
15  
0
2
TCK clock pulse width measured at 1.4V  
TCK rise and fall times  
ns  
3
2
ns  
4
4
spec obsolete, intentionally omitted  
TRST assert time  
5
25  
4
20  
19  
12  
9
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
1
6
Boundary-scan input data setup time  
Boundary-scan input data hold time  
TCK to output data valid  
2
7
15  
4
2
8
3,5  
3,4  
9
TCK to output high impedance  
TMS, TDI data setup time  
TMS, TDI data hold time  
3
10  
11  
12  
13  
0
12  
4
TCK to TDO data valid  
5
4
TCK to TDO high impedance  
3
Notes:  
1. TRST is an asynchronous level sensitive signal. Guaranteed by design.  
2. Non-JTAG signal input timing with respect to TCK.  
3. Non-JTAG signal output timing with respect to TCK.  
4. Guaranteed by characterization and not tested.  
5. Minimum spec guaranteed by characterization and not tested.  
Figu re 9 provides th e J TAG clock in pu t tim in g diagram .  
1
2
2
TCK  
VM  
VM  
VM  
3
3
VM = Midpoint Voltage (1.4v)  
Figure 9. JTAG Clock Input Timing Diagram  
18 of 44  
PPC740 and PPC750 Hardware Specifications  
Preliminary and subject to change without notice