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IBM25EMPPC750DBUB2660 参数 Datasheet PDF下载

IBM25EMPPC750DBUB2660图片预览
型号: IBM25EMPPC750DBUB2660
PDF下载: 下载PDF文件 查看货源
内容描述: [RISC Microprocessor, 32-Bit, 266MHz, CMOS, CBGA360, 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360]
分类和应用: 时钟外围集成电路
文件页数/大小: 44 页 / 514 K
品牌: IBM [ IBM ]
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3.1.2.6 L2 Bus Output AC Specifications  
Table 12 provides th e L2 bu s ou tpu t in terface AC tim in g specification s for th e PPC750  
as defin ed in Figu re 8 .  
1
Table 12. L2 Bus Output Interface AC Timing Specifications  
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions" CL = 20 pF3  
L2CR[14-15] is equivalent to:  
2
Num Characteristic  
00  
01  
10  
11  
Unit Notes  
Min Max Min Max Min Max Min Max  
26  
27  
28  
L2SYNC_IN to output  
valid  
5.0  
5.5  
Rsv5  
Rsv5 ns  
L2SYNC_IN to output  
hold  
0.5  
1.0  
Rsv5  
Rsv5  
ns  
4
6
L2SYNC_IN to high  
impedance  
4.0  
4.5  
Rsv5  
Rsv5 ns  
Notes:  
1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint  
voltage (1.4 V) of the signal in question. The output timings are measured at the pins.  
2.The outputs are valid for both single-ended and differential L2CLK modes. For flow-thru and pipelined  
reg-reg synchronous burst SRAMs, L2CR[14-15] = 00 is recommended. For pipelined late-write syn-  
chronous burst SRAMs, L2CR[14-15] = 01 is recommended.  
3. All maximum timing specifications assume CL = 20 pF.  
4. This measurement assumes CL= 5 pF.  
5. Reserved for future use.  
6. Guaranteed by design and characterization, and not tested.  
Figu re 8 sh ows th e L2 bu s ou tpu t tim in g diagram s for th e PPC750.  
VM  
VM  
L2SYNC_IN  
26  
27  
ALL OUTPUTS  
L2DATA BUS  
28  
VM = Midpoint Voltage (1.4V)  
Figure 8. L2 Bus Output Timing Diagrams  
PPC740 and PPC750 Hardware Specifications  
17 of 44  
Preliminary and subject to change without notice  
 
 
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