3.1.2.4 L2 Clock AC Specifications
Table 10 provides th e L2CLK ou tpu t AC tim in g specification s for th e PPC740 an d
PPC750 as defin ed in Figu re 6 .
Table 10. L2CLK Output AC Timing Specifications
Operating conditions are specified in Section Table 2., "Recommended Operating Conditions"
Num
Characteristic
Min
Max
Unit
Notes
L2CLK frequency
80
133
12.5
50
MHz
1,5
22
23
L2CLK cycle time
L2CLK duty cycle
L2CLK jitter
7.5
ns
%
2
±150
ps
3,6
4
Internal DLL-relock time
640
—
L2CLK
Notes:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The internal design supports
higher L2CLK frequencies; however, the L2 I/O drivers have been designed to support a 133 MHz L2
bus loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond 133
MHz would require tightly coupled customized SRAMs or a multi-chip module (MCM) implementation.
The L2CLK frequency to core frequency settings must be chosen such that the resulting L2CLK fre-
quency and core frequency do not exceed their respective maximum or minimum operating frequen-
cies. L2CLKOUTA and L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The total input jitter (short term and long term combined) must be under ± 150 ps.
4. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by
the period of L2CLK to compute the actual time duration in nanoseconds. Re-lock timing is guaran-
teed by design and characterization, and is not tested.
5. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
6. Guaranteed by design and characterization, and not tested.
14 of 44
PPC740 and PPC750 Hardware Specifications
Preliminary and subject to change without notice
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