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IBM25CPC945CQ3C-2 参数 Datasheet PDF下载

IBM25CPC945CQ3C-2图片预览
型号: IBM25CPC945CQ3C-2
PDF下载: 下载PDF文件 查看货源
内容描述: [Micro Peripheral IC, CMOS, PBGA1182,]
分类和应用:
文件页数/大小: 69 页 / 1861 K
品牌: IBM [ IBM ]
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Datasheet  
CPC945 Bridge and Memory Controller  
Preliminary  
Table 4-6. Processor Interface 1 Signal Pins  
I/O  
Supply  
Voltage  
Signal  
Levels  
Signal Name  
Signal Description  
Signal Type  
Input  
PI input data from processors 2, 3 on bus 1. ADO[0:43] represents  
the address, data, and control information which can be balanced  
code encoded or 36-bit unencoded signal plus 8-bit parity bits.  
When data transmitted unencoded, ADO[0:35] = data,  
PI1_ADO[0:43]  
1.3 V - 1.5 V  
VDD2  
ADO[36] = transfer handshake, and ADO[37:43] = parity.  
PI1_SROP[0:1]  
PI1_SRON[0:1]  
Snoop coherency response from processors 2, 3 to the CPC945  
Complementary signals to PI1_SROP[0:1]  
Input  
Input  
1.3 V - 1.5 V  
1.3 V - 1.5 V  
VDD2  
VDD2  
BCLKO is the differential bus clock input from the transmitting  
agent used to strobe incoming data by the receiver.  
PI1_BCLKOP  
PI1_BCLKON  
Input  
Input  
1.3 V - 1.5 V  
1.3 V - 1.5 V  
VDD2  
VDD2  
Negative input of the differential bus clock PI1_BCLKP  
PI output data to processors 2, 3 on bus 1. ADI[0:43] represents  
the address, data and control information which can be balanced  
code encoded or 36-bit unencoded signal plus 8-bit parity bits.  
When data transmitted unencoded, ADI[0:35] = data,  
PI1_ADI[0:43]  
Output  
1.3 V - 1.5 V  
VDD2  
ADI[36] = transfer handshake, and ADI[37:43] = parity.  
The snoop response output is the accumulated snoop coherency  
response from the CPC945 to processor 2, 3.  
PI1_SRIP[0:1]  
PI1_SRIN[0:1]  
Output  
Output  
1.3 V - 1.5 V  
1.3 V - 1.5 V  
VDD2  
VDD2  
Complementary signals to PI1_SRIP[0:1]  
The positive differential bus clock sent from the CPC945 to the  
PowerPC 970xx processor 1. The clock is used by processor 1 to  
strobe incoming data.  
BCLKI is the differential bus clock from the transmitting agent  
used to strobe incoming data by the receiver. PI_BCLKIP is the  
positive output from the CPC945 to processor bus 1.  
PI1_BCLKIP  
Output  
1.3 V - 1.5 V  
VDD2  
The negative output of PI0_BCLKIP to processor bus 1 from the  
CPC945  
PI1_BCLKIN  
Output  
1.3 V - 1.5 V  
VDD2  
Note: For the processor interface 1, the driver impedance is controllable to 20 Ω and 40 Ω. The receiver has a 90 Ω termination that  
can be deactivated. See the CPC 945 Bridge and Memory Controller User Manual for more information.  
Table 4-7. Processor Interface Support Signal Pins  
I/O  
Signal  
Type  
Signal  
Levels  
Signal Name  
PI0_APSYNC  
Signal Description  
Supply Notes  
Voltage  
PI clocking signal used to provide system-wide synchronization.  
This pin is an input from a clock chip which generates the appro-  
priate timing for CPC945 and each processor.  
Input  
1.3 V - 1.5 V VDD2  
PI1_APSYNC  
PI_CSTP  
PI0_SE  
This signal is unused and should be left floating.  
PI checkstop  
Output  
I/O  
1.3 V - 1.5 V VDD2  
1.3 V - 1.5 V VDD2  
1.3 V - 1.5 V VDD2  
1.3 V - 1.5 V VDD2  
1
Logic analyzer trigger 0  
Output  
Output  
PI1_SE  
Logic analyzer trigger 1  
Note:  
1. Recommended pull-up resistor = 1.0 kΩ.  
Dimensions and Pin Information  
Page 40 of 69  
A15-6009-03  
December 18, 2007 - IBM Confidential  
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