Datasheet
Preliminary
CPC945 Bridge and Memory Controller
Table 4-3. DDR SDRAM Signal Pins (Page 2 of 2)
I/O
Supply
Voltage
Signal
Type
Signal
Levels
Signal Name
Signal Description
Voltage reference for DDR_DQ[16:31] and DDR_DQS[2:3].
See DDR_VREF_0_1 for implementation details.
DDR_VREF_2_3
DDR_VREF_4_16
Reference 0.5 × VDD3 VDD3
Reference 0.5 × VDD3 VDD3
Voltage reference for DDR_DQ[32:39] and DDR_DQS[4],
DDR_DQ[128:135] and DDR_DQS[16].
See DDR_VREF_0_1 for implementation details.
Voltage reference for DDR_DQ[40:55] and DDR_DQS[5:6].
See DDR_VREF_0_1 for implementation details.
DDR_VREF_5_6
DDR_VREF_7_8
DDR_VREF_9_10
Reference 0.5 × VDD3 VDD3
Reference 0.5 × VDD3 VDD3
Reference 0.5 × VDD3 VDD3
Voltage reference for DDR_DQ[56:71] and DDR_DQS[7:8].
See DDR_VREF_0_1 for implementation details.
Voltage reference for DDR_DQ[72:87] and DDR_DQS[9:10].
See DDR_VREF_0_1 for implementation details.
Voltage reference for DDR_DQ[88:95] and DDR_DQS[11],
DDR_DQ[136:143] and DDR_DQS[17].
DDR_VREF_11_17
Reference 0.5 × VDD3 VDD3
See DDR_VREF_0_1 for implementation details.
Voltage reference for DDR_DQ[112:127] and DDR_DQS[14:15].
See DDR_VREF_0_1 for implementation details.
DDR_VREF_12_13
DDR_VREF_14_15
Reference 0.5 × VDD3 VDD3
Reference 0.5 × VDD3 VDD3
Voltage reference for DDR_DQ[96:111] and DDR_DQS[12:13].
See DDR_VREF_0_1 for implementation details.
DDR_CK_A
DDR_CK_AN
DDR_CK_B
Positive output of the differential clock to bank 0 of the SDRAM
Negative output of the differential clock to bank 0 of the SDRAM
Positive output of the differential clock to bank 1 of the SDRAM
Negative output of the differential clock to bank 1 of the SDRAM
SDRAM clock enables
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
DDR_CK_BN
DDR_CKE[0:7]
DDR_CS[0:15]
DDR_BA[0:2]
DDR_MAD[0:15]
DDR_RAS
SDRAM chip selects
SDRAM bank address
Address input to SDRAM
Memory command, row enables
DDR_CAS
Memory command, column enables
DDR_WE
Memory commands, write enables
DDR_MUXEN[0:7]
DDR_ODT[0:7]
Multiplexer selects for data external data multiplexer
8 bits of the on-die termination (ODT)
A15-6009-03
December 18, 2007 - IBM Confidential
Dimensions and Pin Information
Page 37 of 69
IBM [ IBM ]
