Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Table 4-2. PCIe Signal Pins
I/O
Supply
Voltage
Signal
Type
Signal
Levels
Signal Name
Signal Description
PCIE_HSOP[15:0]
PCIE_HSON[15:0]
PCIE_HSIP[15:0]
PCIE_HSIN[15:0]
PCI Express transmit bus - positive differential signal
PCI Express transmit bus - negative differential signal
PCI Express receive bus - positive differential signal
PCI Express receive bus - negative differential signal
Output
Output
Input
1.5 V
1.5 V
1.5 V
1.5 V
VDD
VDD
VDD
VDD
Input
PCIE_AV25_0
PCIE_AV25_1
PCIE_AV25_2
Analog
Power
PCI Express physical layer (PHY) analog voltage regulator input
1.65 - 2.75 V N/A
PCIE_AVREG_0
PCIE_AVREG_1
PCIE_AVREG_2
PCI Express PHY analog voltage regulator monitor output, test only
Calibration resistor input
Output
N/A
N/A
PCIE_UCAL_RES0
PCIE_UCAL_RES1
Reference
Input
N/A
N/A
Slot present, an open drain with external pull up. A low input indicates
that a PCIe card is present.
PCIE_PRESENTN
2.5 V
VDD5
Table 4-3. DDR SDRAM Signal Pins (Page 1 of 2)
I/O
Supply
Voltage
Signal
Type
Signal
Levels
Signal Name
Signal Description
DDR random access memory data bus [0:143], 128 bits of data, 16 bits
of ECC
DDR_DQ[0:143]
I/O
1.8 V
VDD3
Positive I/O of the differential data strobes DQS[0:17] for
DDR_DQ[0:143]:
DDR_DQ[0:7] - DDR_DQS[0],
DDR_DQ[8:15] - DDR_DQS[1],
DDR_DQ[16:23] - DDR_DQS[2],
DDR_DQ[24:31] - DDR_DQS[3],
DDR_DQ[32:39] - DDR_DQS[4],
DDR_DQ[40:47] - DDR_DQS[5],
DDR_DQ[48:55] - DDR_DQS[6],
DDR_DQ[56:63] - DDR_DQS[7],
DDR_DQ[64:71] - DDR_DQS[8],
DDR_DQ[72:79] - DDR_DQS[9],
DDR_DQ[80:87] - DDR_DQS[10],
DDR_DQ[88:95] - DDR_DQS[11],
DDR_DQ[96:103] -DDR_DQS[12],
DDR_DQ[104:111] - DDR_DQS[13],
DDR_DQ[112:119] - DDR_DQS[14],
DDR_DQ[120:127] - DDR_DQS[15],
DDR DQ[128:135] - DDR_DQS[16],
DDR DQ[136:143] - DDR_DQS[17]
DDR_DQSP[0:17]
I/O
1.8 V
VDD3
DDR_DQSN[0:17]
DDR_VREF_0_1
Negative I/O of the differential data strobes DQS[0:17]
I/O
1.8 V
VDD3
Voltage reference for DDR_DQ[0:15] and DDR_DQS[0:1].
VREF is typically generated using external low value (<1 kΩ),
1% precision resistors. These voltage references should also be
bypassed to ground with a capacitor to track any ground noise. The ref-
erence voltages must be stable and low noise. The input current into the
VREF pins is negligible.
Reference 0.5 × VDD3 VDD3
Dimensions and Pin Information
Page 36 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
IBM [ IBM ]
