Datasheet
CPC945 Bridge and Memory Controller
Preliminary
Table 4-4. HyperTransport Signal Pins
I/O
Signal
Type
Signal
Levels
Signal Name
Signal Description
Supply Notes
Voltage
Differential signal for command, address and data bus transmitter
(positive)
HT_CAD_TXP[0:15]
HT_CAD_TXN[0:15]
Output
Output
1.2 V
1.2 V
VDD4
VDD4
Differential signal for command, address and data bus transmitter
(negative)
HT_CLK_TXN[0:1] The negative differential clock signals for the HT_CAD_TX signals
Output
Output
1.2 V
1.2 V
VDD4
VDD4
HT_CLK_TXP[0:1]
The positive differential clock signals for the HT_CAD_TX signals
The positive differential signal for control transmitter
HT_CTL_TXP0
HT_CTL_TXP1
Output
Output
1.2 V
1.2 V
VDD4
VDD4
HT_CTL_TXN0
HT_CTL_TXN1
The negative differential signal for control transmit
HT_PWROK
HT_RESET_L
HT_LDTSTOP_L
HT_LDTREQ_L
HyperTransport power OK
I/O
I/O
I/O
I/O
2.5 V
2.5 V
2.5 V
2.5 V
VDD5
VDD5
VDD5
VDD5
1
1
1
1
HyperTransport reset
HyperTransport power-down request
Reenabling link for normal operation
The positive differential signal for command, address, and data
bus receive
HT_CAD_RXP[0:15]
HT_CAD_RXN[0:15]
Input
Input
1.2 V
1.2 V
VDD4
VDD4
The negative differential signal for command, address, and data
bus receive
HT_CLK_RXP[0:1] The positive differential signal for CAD[0:7] clock receiver
HT_CLK_RXN[0:1] The negative differential signal for CAD[0:7] clock receiver
Input
Input
1.2 V
1.2 V
VDD4
VDD4
HT_CTL_RXP0
The positive differential signal for control receive
HT_CTL_RXP1
Input
Input
1.2 V
1.2 V
N/A
VDD4
VDD4
N/A
HT_CTL_RXN0
The negative differential signal for control receive
HT_CTL_RXN1
HT_PVTREF0
HT_PVTREF1
This I/O requires an external 100 Ω precision resistor between
HT_PVTREF0 and HT_PVTREF1
Reference
Reference
HT_PVTREF2
HT_PVTREF3
This I/O requires an external 200 Ω precision resistor between
HT_PVTREF2 and HT_PVTREF3
N/A
N/A
Note:
1. Recommended pull-up resistor = 4.7 kΩ.
Dimensions and Pin Information
Page 38 of 69
A15-6009-03
December 18, 2007 - IBM Confidential
IBM [ IBM ]
