Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
I/O Specifications—100 MHz (Part 2 of 2)
Notes:
1. Output Valid from SYS_CLK
2. Output Hold from SYS_CLK
3. All inputs are referenced to the rising edge of SYS_CLK.
Input (ns)
Output (ns)
Valid
Hold
Signal
Notes
Setup
Hold
(T min)
Load
(pf)
Load
(pf)
(T min)
IS
IH
Max
Min
SIO Interface
FLASH_CE
FLASH_OE
FLASH_WE
PRES_OE0:1
XADR_LAT
XCVR_RD
nana8.1
80
0.8
5
1,
2
nana5.4
nana6.9
nana6.2
20
25
25
1
1
1
5
5
5
1,
1,
1,
2
2
2
Note: Refer to P_ADL31:0 signals in the PCI-32 section for FLASH address and data signal I/O timing.
PCI Interface (See “PCI I/O Specifications—133 MHz” on page 52)
51
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