Preliminary
CPC710 PCI Bridge and Memory Controller Data Sheet
PCI I/O Specifications—133 MHz
Notes:
1. Output Valid from PCI_CLK
2. Input Setup to PCI_CLK
3. Input Hold from PCI_CLK
4. Output Valid from PCG_CLK
5. Input Setup to PCG_CLK
6. Input Hold from PCG_CLK
Input (ns)
Output Valid (ns)
Max
Signal
Notes
Setup
Hold
Min
Load (pf)
(T min)
(T min)
IS
IH
PCI-32 Interface @ 33 MHz
P_ADL31:00
P_CBE3:0
P_DEVSEL
P_FRAME
P_IRDY
7
0.5
2.6
11
50
1, 2, 3
P_PAR
P_PERR
P_SERR
P_STOP
P_TRDY
P_LOCK
nananana50
P_GNT0:3
P_MEMACK
P_REQ0:6
P_MEMREQ
PCI-64 Interface @ 66 MHz
G_ADH31:0
G_ADL31:0
G_CBE7:0
G_ACK64
G_REQ64
G_DEVSEL
G_FRAME
G_IRDY
nana3.2
nana4.4
12
12
50
30
1
1
3
5
0.5
0
nanana2,
nanananana2,
3
1.8
2
7.4
10
4, 5, 6
3
0
0
0
0
0
0
2
2
2
2
2
2
6.9
6.4
7.2
6
10
10
10
10
10
10
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
3.8
2.1
3.8
3.4
6.4
6
4.3
G_LOCK
nananana10
G_PAR
2.8
2.1
1
0
0
0
0
0
0
nana10
4,
6.6
5,
10
6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
G_PAR64
G_PERR
2
2
2
2
2
6.3
10
G_SERR
1.8
3
6.5
10
G_STOP
6.6
10
G_TRDY
3.6
6.5
10
G_GNT0:2
G_GNT4:7
G_GNT3
nana 2
6.4
6
10
4
nana 2
1.8
10
4
6
6
G_IDSEL
0
0
nanana5,
nanana5,
G_REQ0:7
4.3
52
IBM [ IBM ]
