IBM PowerPC 403GCX
DRAM Interface Timing Diagram
ADDRESS
T
T
T
ASC
T
T
T
RP
ASR
RAH
CAH
RAS
RAS
CAS
T
T
CP
CAS
1.5V
T
DS
WRITE DATA
Output Derating for Capacitance and Voltage
Output Propagation Delay Derating
Note: Test Conditions
Derating Equations for Output Delays:
Vt = 1.5V at TJ = 85°C
1. ∆tpLH(CL, V) = tpLH C + tpLH
+20
V
tpZL C = 0.14 CL - 1.2ns
∆
∆
∆
∆
(from 5.5V)
2. ∆tpHL(CL, V) = tpHL C + tpHL
V
∆
3. ∆tpZL5V(CL, V) = tpZL C + tpHL
V
∆
∆
+10
tpHL C = 0.06 CL - 2.3ns
∆
tpLH C = 0.04 CL - 1.9ns
∆
0
-10
150
0
100
(pF)
50
C
L
33