IBM16M32644HGA
IBM16M32734HGA
IBM16M64644HGA
IBM16M64734HGA
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
Preliminary
Wiring and Topology
This section contains the information needed to understand the timing relationships presented in the AC
Characteristics section. Because the system designer must measure all signals at the first receiving device
(SDRAM DQ pin for data, register input pin for address and controls, and PLL check input pin for clock), the
following pages provide detailed information on these inputs. In some cases DIMM timing adjustments are
listed in the specifications, and in some cases it is recommended that the customer determine this informa-
tion via simulation. This section enables the customer to understand the device pinouts on the DIMM, the net
structures, and the loading associated with these devices. For detailed timing analysis, contact an IBM Mar-
keting Representative for simulation models. System-level modeling is strongly recommended to determine
delay adders of the entire net structure in the customer’s application.
Pin Assignments for the 256 Mbit DDR SDRAM Planar Component (top view)
VDD
DQ0
VDDQ
NC
VSS
1
2
3
4
5
66
65
64
63
62
DQ7
VSSQ
NC
DQ6
DQ1
VDDQ
NC
VSSQ
NC
6
61
60
59
58
57
7
DQ5
VSSQ
NC
DQ2
VDDQ
NC
8
9
10
DQ3
DQ4
11
12
56
55
VSSQ
NC
VDDQ
NC
13
14
15
16
17
18
19
20
54
53
52
51
50
49
48
47
NC
NC
VSSQ
DQS
NC
VDDQ
NC
NC
VDD
NU
VREF
VSS
DM
NC
WE
CK
CK
21
22
23
46
45
44
CAS
RAS
CKE
CS
NC
NC
24
25
43
42
A12
BA0
BA1
A11
A9
26
27
41
40
A8
A10/AP
28
29
39
38
A7
A0
A1
A2
A6
A5
30
31
37
36
A3
A4
32
33
35
34
VDD
VSS
66-pin Plastic TSOP-II 400mil
32Mb x 8 x 4 Bank
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7358.H02502
3/00
Page 20 of 28
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