IBM16M32644HGA
IBM16M32734HGA
IBM16M64644HGA
IBM16M64734HGA
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
Preliminary
Operating, Standby, and Refresh Currents (0 ˚C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V,
See AC Characteristics)
x72
x64
Symbol
Parameter/Condition
Unit
mA
Notes
1, 2
2 Bank 1 Bank 2 Bank 1 Bank
Operating Current: one bank; active / precharge; t
=
RC
t
; t = t
; DQ, DM, and DQS inputs changing
RC MIN CK
CK MIN
I
I
TBD
TBD
TBD
TBD
DD0
DD1
twice per clock cycle; address and control inputs changing
once per clock cycle
Operating Current: one bank; active / read / precharge;
Burst = 2; t = t
; CL = 2.5; t = t
; I
=
RC
RC MIN
CK
CK MIN OUT
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
1, 2
1, 2
1, 2
0mA; address and control inputs changing once per clock
cycle
Precharge Power-Down Standby Current: all banks
I
DD2P
idle; power-down mode; CKE ≤ V
; t = t
IL MAX CK
CK MIN
Idle Standby Current: CS ≥ V
; all banks idle; CKE ≥
IH MIN
V
t
;
IH MIN
I
DD2N
= t
; address and control inputs changing once
CK
CK MIN
per clock cycle
Active Power-Down Standby Current: one bank active;
I
power-down mode;
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
1, 2
1, 2
DD3P
CKE ≤ V
; t = t
IL MAX CK
CK MIN
Active Standby Current: one bank; active / precharge;
CS ≥ V
;
IH MIN
I
I
CKE ≥ V
; t = t
; t = t
; DQ, DM, and
DD3N
IH MIN RC
RAS MAX CK
CK MIN
DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continu-
ous burst; address and control inputs changing once per
clock cycle; DQ and DQS outputs changing twice per
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
1, 2
1, 2
DD4R
clock cycle; CL = 2.5; t = t
; I
= 0mA
CK
CK MIN OUT
Operating Current: one bank; Burst = 2; writes; continu-
ous burst; address and control inputs changing once per
clock cycle; DQ and DQS inputs changing twice per clock
I
DD4W
cycle; CL = 2.5; t = t
CK
CK MIN
I
I
Auto-Refresh Current: t = t
RFC MIN
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
1, 2
DD5
DD6
RC
Self-Refresh Current: CKE ≤ 0.2V
1, 2, 3
1. I specifications are tested after the device is properly initialized.
DD
2. Input slew rate = 1V/ns.
3. Enables on-chip refresh and address counters.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7358.H02502
3/00
Page 16 of 28
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