IBM16M64644HGA
IBM16M64734HGA
IBM16M32644HGA
IBM16M32734HGA
Preliminary
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
The table below describes the DQ and CB wiring information for each SDRAM on the DIMM. Note that the
DQ wiring is different from that described in the Block Diagram.
SDRAM Wiring Information
1
Device Position to DIMM Tab I/O
DQ SDRAM DQ SDRAM
Designator Pin Number
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
2
3
7
2
6
5
1
4
0
8
23
19
22
18
21
17
16
20
24
28
25
29
30
26
27
31
32
36
33
37
38
34
39
35
43
47
42
46
41
45
44
40
48
52
49
53
54
50
55
51
59 CB3
63 CB7
58 CB2
62 CB6
57 CB1
61 CB0
56 CB5
60 CB4
0
4
1
5
6
2
7
3
11
15
10
14
13
9
20
16
17
21
18
22
19
23
31
27
26
30
29
25
28
24
35
39
34
38
37
33
36
32
40
44
45
41
46
42
47
43
51
55
50
54
53
49
52
48
60 CB4
56 CB5
61 CB0
57 CB1
62 CB6
58 CB2
63 CB7
59 CB3
5
12
9
8
11
56
59
62
65
13
14
10
15
11
12
8
1. These numbers can be associated with the corresponding DIMM tab pin by referencing the DIMM connector pinout on pages 5
and 6 of this document. Example: DQ7 at the DIMM tab (pin 99) is wired to SDRAM device position D0, pin 5 and D9, pin 62.
Note: 64Mx72 uses DDR SDRAM device positions D0-D17
64Mx64 uses D0-D15 only
32Mx72 uses D0-D8 only
32Mx64 uses D0-D7 only
Data, CB, DQS, and DM Net Structures
TL2
SDRAM Pin
22 Ω 2%
TL0
TL1
DIMM
Connector
TL2
for 2 Bank
DIMMs only
SDRAM Pin
Note: Transmission Lines (TL) are represented as cylinders and are labeled with length designators. These
are the only lines which represent physical trace segments. For more detailed topology information please
refer to the DDR SDRAM Registered DIMM Design Specification.
Trace Lengths for Data Net Structure
TL0
TL1
TL2
Total
Unit
Min
Max
Min
Max
Min
Max
Min
Max
0.125
0.193
0.581
0.670
0.370
0.439
1.145
1.296
inches
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7358.H02502
3/00
Page 21 of 28
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