IBM16M64644HGA
IBM16M64734HGA
IBM16M32644HGA
IBM16M32734HGA
Preliminary
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
Electrical Characteristics & AC Timing
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 3 of 3)
PC266B
PC200
Symbol
Parameter
Active to Precharge command
Unit Notes
Min
Max
Min
50
70
80
20
20
15
15
Max
t
45
65
75
20
20
15
15
120,000
120,000
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
RAS
t
Active to Active/Auto-refresh command period
Auto-refresh to Active/Auto-refresh command period
Active to Read or Write delay
RC
t
RFC
RCD
t
t
Precharge command period
RP
RRD
t
Active bank A to Active bank B command
Write recovery time
t
WR
DAL
WTR
Auto precharge write recovery
+ precharge time
t
35
35
ns
1, 2, 3
t
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
1
1
t
1, 3
1, 3
CK
t
t
75
80
ns
XSNR
XSRD
200
200
t
1, 3
CK
t
7.8
7.8
µs
1, 3, 8
REFI
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level
for signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
stabilizes.
REF
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
.
TT
5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
HZ
LZ
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending on t
.
DQSS
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. This parameter is specified at the SDRAM. For system-level timing analysis, the on-DIMM clock skew must be included in addition
to the SDRAM timing parameter (0.20ns).
10. This command is specified at the SDRAM. For system-level timing analysis simulation of the DIMM design file is highly recom-
mended. This simulation will take into account DIMM adders to the specified values.
11. This parameter is specified at the register input receiver and includes DIMM-related timing adjustments. Simulation with the DIMM
design file is highly recommended.
12. The time from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input sig-
nal.
13. The time in which the system must maintain valid levels on the clocks and address and control signals after the RESET low has
been applied.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7358.H02502
3/00
Page 19 of 28
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