IBM16M64644HGA
IBM16M64734HGA
IBM16M32644HGA
IBM16M32734HGA
Preliminary
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
The table below describes the address and control information for each signal on the DIMM.
Register Input Wiring
Register Pin Number
Register 1 Signal
Register 2 Signal
Notes
1
25
26
29
30
31
32
33
40
41
42
43
44
47
48
NC
CKE1
CKE0
A12
A11
A9
A0
A10
BA1
NC
BA0
RAS
WE
NC
A7
A8
A5
NC
A6
NC
A4
SI
1
A3
CAS
S0
A2
A1
NC
1. CKE1 and SI register inputs are grounded and are NC at the DIMM connector in the single bank cases.
Address/Control Signal Net Structure
TL0
22 Ω
TL1
DIMM
Connector
Register
Trace Lengths
TL0
TL1
Units
Min
Max
Min
0.563
Max
0.665
0.131
0.225
inches
Note: Each signal has one register input load in order to aid in system level timings.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L7358.H02502
3/00
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