IBM16M32644HGA
IBM16M32734HGA
IBM16M64644HGA
IBM16M64734HGA
32/64Mx64/72 1 or 2 Bank Registered DDR SDRAM Module
Preliminary
The table below describes the input wiring for each clock on the DIMM.
Clock Input Wiring
CK0, CK0
CK1, CK1, CK2, CK2
NC
PLL CLK input pin 13, 14
Clock Topology
TL0
Phase
CK0
Locked
Loop (PLL)
CK0
DIMM
Connector
TL1
R1
Trace Lengths
TL0
TL1
R1 [ohms]
120
Unit
inches
1.00
0.066
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Use is further subject to the provisions at the end of this document.
19L7358.H02502
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