IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
EDO Page Mode Read Cycle (OE Control)
tRP
tRASP
VIH
RAS
tCPRH
VIL
tCRP
tHPC
tRCD
tCP
tCP
tRSH
tHCAS
tHCAS
tHCAS
VIH
CAS
VIL
tCSH
tRAL
tCAH
tASR tRAH
tASC
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tRAD
tRCH
tRRH
tWRH
tWRP
tRCS
VIH
VIL
WE
NOTE 1
tCAC
tCAC
tCPA
tOFF
tCPA
tOES
tOEA
tAA
tAA
tOES
tOEHC
tOEP
tOES
tOEHC
tOEP
VIH
VIL
OE
tOEZ
tRAC
tAA
tOEA
tOEA
tCAC
tCLZ
tOEZ
tOEZ
VOH
VOL
DOUT
Hi-Z
Data Out 1
Data Out 2
Data Out N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 18 of 33
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