IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
EDO Page Mode Late Write Cycle
tRP
tRASP
VIH
RAS
VIL
tHPC
tCRP
tRCD
tCP
tCP
tRSH
tHCAS
VIH
CAS
tHCAS
tHCAS
VIL
tRAD
tASR tRAH
tCSH
tASC
tCAH
tASC
tCAH
tASC
tCAH
VIH
VIL
Address
Row
Column 1
Column 2
Column N
tCWL
tCWL
tCWL
tWRH
tWRP
tRCS
tRCS
tRWL
tWP
tRCS
tWP
tWP
VIH
VIL
WE
NOTE 1
tOEH
tOEH
tOEH
VIH
VIL
OE
tODD
tDS
tDH
tODD
tDS
tDH
tODD
tDS
tDH
VIH
VIL
DIN
Hi-Z
Data In 1
Data In 2
Data In N
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 21 of 33
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