IBM11N1645L
IBM11N1735Q
1M x 64/72 DRAM Module
EDO Page Mode Read Modify Write Cycle
tRP
tRASP
VIH
RAS
VIL
tHPRWC
tCRP
tCP
tCP
tRCD
VIH
CAS
tCAS
tCAS
tCAS
VIL
tCSH
tASC
tASC
tRAD
tRAH
tRAL
tASR
tASC
tCAH
tCAH
tCAH
VIH
Address
Column 1
Column 2
Column N
Row
VIL
tCWL
tRWL
tCPA
tAA
tCPA
tAA
tCWL
tRWD
tAWD
tCWD
tWRP
tWRH
tAWD
tCWD
tAWD
tCWD
tRCS
tRCS
tRCS
tWP
tWP
tWP
VIH
VIL
WE
OE
NOTE 1
tCAC
tRAC
tAA
tCAC
tCAC
tOEH
tOEH
tOEA
tOEH
tOEA
VIH
VIL
tOEA
tODD
tODD
tODD
tCLZ
tOEZ
DOUT
tDS
tOEZ
DOUT
tDS
tOEZ
tCLZ
tCLZ
VOH
VOL
DOUT
Hi-Z
Hi-Z
DOUT
tDS
tDH
DIN
tDH
DIN
tDH
DIN
VIH
VIL
DIN
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
50H8035
SA14-4630-02
Revised 5/96
Page 22 of 33
IBM [ IBM ]
