IBM0625404GT3B IBM0625164GT3B
IBM0625804GT3B IBM06254B4GT3B
256Mb Double Data Rate Synchronous DRAM
Advance
Electrical Characteristics & AC Timing for PC266/PC200 - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
PC266A
Min
PC266B
Min
PC200
Min
Symbol
Parameter
Unit Notes
Max
+ 0.75
+ 0.75
0.55
0.55
15
Max
+ 0.75
+ 0.75
0.55
0.55
15
Max
+ 0.8
+ 0.8
0.55
0.55
15
t
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
− 0.75
− 0.75
0.45
0.45
7
− 0.75
− 0.75
0.45
0.45
7.5
− 0.8
− 0.8
0.45
0.45
8
ns
ns
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
AC
t
DQSCK
t
t
CH
CK
CK
t
CK low-level width
t
CL
CK
CK
DH
t
t
CL = 2.5
Clock cycle time
ns
ns
ns
ns
ns
CL = 2.0
7.5
15
8
15
10
15
t
DQ and DM input hold time
0.5
0.5
0.6
0.6
2
t
DQ and DM input setup time
0.5
0.5
DS
t
DQ and DM input pulse width (each input)
1.75
1.75
DIPW
Data-out high-impedence time from
CK/CK
t
− 0.75
− 0.75
− 0.5
+ 0.75
+ 0.75
− 0.75
− 0.75
− 0.5
+ 0.75
+ 0.75
− 0.8
− 0.8
− 0.6
+ 0.8
+ 0.8
ns 1-4, 5
ns 1-4, 5
HZ
Data-out low-impedence time from
CK/CK
t
LZ
DQS-DQ skew (DQS & associated DQ sig-
nals)
t
+ 0.5
+ 0.5
+ 0.5
+ 0.5
+ 0.6
+ 0.6
ns
ns
1-4
DQSQ
t
DQS-DQ skew (DQS & all DQ signals)
DQ/DQS output valid time
− 0.5
− 0.5
− 0.6
1-4
1-4
DQSQA
t
0.35
0.35
0.35
t
DV
CK
CK
CK
CK
Write command to 1st DQS latching
transition
t
0.75
0.35
0.2
1.25
0.75
0.35
0.2
1.25
0.75
0.35
0.2
1.25
t
t
t
1-4
1-4
1-4
DQSS
t
DQS input low (high) pulse width (write cycle)
DQSL,H
DQS falling edge to CK setup time (write
cycle)
t
DSS
DQS falling edge hold time from CK (write
cycle)
t
0.2
0.2
0.2
t
1-4
1-4
DSH
CK
t
Mode register set command cycle time
Write preamble setup time
14
0
15
0
16
0
ns
MRD
t
ns 1-4, 7
WPRES
1. Input slew rate = 1V/ns
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for
signals other than CK/CK, is V
REF.
3. Inputs are not recognized as valid until V
stabilizes.
REF
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
.
TT
5. t and t transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
HZ
LZ
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in
progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH,
LOW, or transitioning from HIGH to LOW at this time, depending on t
.
DQSS
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. QFC is enabled as soon as possible after the rising CK edge that registers the Write command.
10. QFC is disabled as soon as possible after the last valid DQS edge transitions Low.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
29L0011.E36997
10/99
Page 56 of 75
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